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rev. 1.2 6/12 copyright ? 2012 by silicon laboratories si860x si860x b idirectional i 2 c i solators with u nidirectional d igital c hannels features applications description the si860x series of isolators are single-package galvanic isolation solutions for i 2 c and smbus serial port applications. thes e products are based on silicon labs proprietary rf isolation technology and offer shorter propagation delays, lower power consumption, smaller installed size, and more stable operation with temperature and age versus opto coup lers or other digital isolators. all devices in this family include hot-swap, bidirectional sda and/or scl isolation channels with open-drain, 35 ma sink capability that operate to a maximum frequency of 1.7 mhz. the 8-pin version (si8600) supports bidirectional sda and scl isolation; the si8602 supports bidirectional sda and unidirectional scl isolation, and the 16-pin versions (s i8605, si8606) featur e two unidirectional isolation channels to su pport additional system signals, such as interrupts or resets. all versions contain protection circuits to guard against data errors when an unpowered device is insert ed into a powered system. small size, low installed cost, low power consumption, and short propagation delays make the si860x family the optimum solution for isolating i 2 c and smbus serial ports. safety regulatory approval ? independent, bidirectional sda and scl isolation channels ?? open drain outputs with 35 ma sink current ?? supports i 2 c clocks up to 1.7 mhz ? unidirectional isolation channels support additional system signals (si8605, si8606) ? up to 5000 v rms isolation ? ul, csa, vde recognition ? 60-year life at rated working voltage ? high electromagnetic immunity ? wide operating supply voltage ?? 3.0 to 5.5 v ? wide temperature range ?? ?40 to +125 c ? transient immunity 50 kv/s ? aec-q100 qualification ? rohs-compliant packages ?? soic-8 narrow body ?? soic-16 wide body ?? soic-16 narrow body ? isolated i 2 c, pmbus, smbus ? power over ethernet ? motor control systems ? hot-swap applications ? intelligent power systems ? isolated smps systems with pmbus interfaces ? ul 1577 recognized ?? up to 5000 v rms for 1 minute ? csa component notice 5a approval ?? iec 60950-1, 61010-1, 60601-1 (reinforced insulation ) ? vde certification conformity ?? iec 60747-5-2 (vde0884 part 2) ?? en60950-1 (reinforced insulation) ordering information: see page 26.
2 rev. 1.2 si860x
rev. 1.2 3 si860x t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 1.1. test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 2.1. theory of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3. typical application o verview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1. i 2 c background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2. i 2 c isolator operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.3. i 2 c isolator design constraints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4. i 2 c isolator design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5. typical application schem atics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4. device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.1. device startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.2. undervoltage lo ckout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3. input and output char acteristics for non-i2c dig ital channels . . . . . . . . . . . . . . . . 20 4.4. layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.5. fail-safe operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 4.6. typical performance char acteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5. pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7. package outline: 16-pin wide body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8. land pattern: 16-pin wide-b ody soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9. package outline: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 10. land pattern: 8-pin narrow body so ic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11. package outline: 16-pi n narrow body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12. land pattern: 16-pin narro w body soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 13. top markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 13.1. si860x top marking (16-pin wide body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 13.2. top marking explanati on (16-pin wide body soic ) . . . . . . . . . . . . . . . . . . . . . . . 35 13.3. si860x top marking (8-pin narr ow body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 13.4. top marking explanati on (8-pin narrow body so ic) . . . . . . . . . . . . . . . . . . . . . . . 36 13.5. si860x top marking (16-pin narrow body soic) . . . . . . . . . . . . . . . . . . . . . . . . . . 37 13.6. top marking explanati on (16-pin narrow body so ic) . . . . . . . . . . . . . . . . . . . . . . 37 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 contact inform ation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
4 rev. 1.2 si860x 1. electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit ambient operating temperature* t a ?40 25 125* c supply voltage avdd 3.0 ? 5.5 v bvdd 3.0 ? 5.5 v *note: the maximum ambient temperature is dependent on data fr equency, output loading, num ber of operating channels, and supply voltage. table 2. si860x power characteristics* 3.0 v < vdd < 5.5 v. ta = ?40 to +125 c. typical specs at 25 c (see figures 2 and 9 for test diagrams.) parameter symbol test condition min typ max unit si8600 supply current avdd current bvdd current idda iddb all channels = 0 dc ? ? 5.4 4.3 7.6 6.5 ma ma avdd current bvdd current idda iddb all channels = 1 dc ? ? 2.6 1.9 3.9 2.9 ma ma avdd current bvdd current idda iddb all channels = 1.7 mhz ? ? 3.3 2.6 5.0 3.9 ma ma si8602 supply current avdd current bvdd current idda iddb all channels = 0 dc ? ? 1.8 1.8 2.7 2.7 ma ma avdd current bvdd current idda iddb all channels = 1 dc ? ? 4.7 3.1 7.1 4.7 ma ma avdd current bvdd current idda iddb all channels = 1.7 mhz ? ? 2.5 2.1 3.8 3.2 ma ma si8605 supply current avdd current bvdd current idda iddb all non-i 2 c channels = 0 all i 2 c channels = 1 ? ? 3.4 2.7 5.1 4.1 ma ma avdd current bvdd current idda iddb all non-i 2 c channels = 1 all i 2 c channels = 0 ? ? 7.2 6.2 10.1 8.7 ma ma avdd current bvdd current idda iddb all non-i 2 c channels = 5 mhz all i 2 c channels = 1.7 mhz ? ? 4.2 3.6 6.3 5.4 ma ma *note: all voltages are relative to respective ground.
rev. 1.2 5 si860x si8606 supply current avdd current bvdd current idda iddb all non-i 2 c channels = 0 all i 2 c channels = 1 ? ? 2.8 3.0 4.2 4.5 ma ma avdd current bvdd current idda iddb all non-i 2 c channels = 1 all i 2 c channels = 0 ? ? 8.3 5.5 11.6 7.7 ma ma avdd current bvdd current idda iddb all non-i 2 c channels = 5 mhz all i 2 c channels = 1.7 mhz ? ? 4.1 3.5 6.2 5.3 ma ma table 3. si8600/02/05/06 electrical characteristics for bidirectional i 2 c channels 1 3.0 v < vdd < 5.5 v. ta = ?40 to +125 c. typical specs at 25 c unless otherwise noted. parameter symbol test condition min typ max unit logic levels side a logic input threshold 2 logic low output voltages input/output logic low level difference 3 i 2 cv t (side a) i 2 cv ol (side a) i 2 c ? v (side a) isdaa, iscla (>0.5 ma, <3.0 ma) 410 540 50 ? ? ? 540 800 ? mv mv mv mv logic levels side b logic low input voltage logic high input voltage logic low output voltage i 2 cv il (side b) i 2 cv ih (side b) i 2 cv ol (side b) isclb = 35 ma ? 2.0 ? ? ? ? 0.8 ? 500 v v mv scl and sda logic high leakage isdaa, isdab iscla, isclb sdaa, scla = vssa sdab, sclb = vssb ?2.010a pin capacitance sdaa, scla, sdab, sdbb ca cb ? ? 10 10 ? ? pf pf notes: 1. all voltages are relative to respective ground. 2. v il < 0.410 v, v ih > 0.540 v. 3. i 2 c ? v (side a) = i 2 cv ol (side a) ? i 2 cv t (side a). to ensure no latch-up on a given bus, i 2 c ? v (side a) is the minimum difference between the output logic low level of the driving device and the input logic threshold. 4. side a measured at 0.6 v. table 2. si860x power characteristics* (continued) 3.0 v < vdd < 5.5 v. ta = ?40 to +125 c. typical specs at 25 c (see figures 2 and 9 for test diagrams.) parameter symbol test condition min typ max unit *note: all voltages are relative to respective ground.
6 rev. 1.2 si860x timing specifications (measured at 1.40 v unless otherwise specified) maximum i 2 c bus frequency fmax ? ? 1.7 mhz propagation delay 5 v operation side a to side b rising 4 side a to side b falling 4 side b to side a rising side b to side a falling 3.3 v operation side a to side b rising 4 side a to side b falling 4 side b to side a rising side b to side a falling tphab tplab tphba tplba tphab tplab tphba tplba no bus capacitance, r1 = 1400, r2 = 499, see figure 2 r1 = 806 r2 = 499 ? ? ? ? ? ? ? ? 38 15 33 11 44 17 30 14 45 26 46 22 55 29 40 27 ns ns ns ns ns ns ns ns pulse width distortion 5v side a low to side b low 4 side b low to side a low 3.3 v side a low to side b low 4 side b low to side a low pwdab pwdba pwdab pwdba no bus capacitance, r1 = 1400, r2 = 499, see figure 2 r1 = 806, r2 = 499 ? ? ? ? 22 21 27 15 32 32 35 25 ns ns ns ns table 3. si8600/02/05/06 electrical characteristics for bidirectional i 2 c channels 1 (continued) 3.0 v < vdd < 5.5 v. ta = ?40 to +125 c. typical specs at 25 c unless otherwise noted. parameter symbol test condition min typ max unit notes: 1. all voltages are relative to respective ground. 2. v il < 0.410 v, v ih > 0.540 v. 3. i 2 c ? v (side a) = i 2 cv ol (side a) ? i 2 cv t (side a). to ensure no latch-up on a given bus, i 2 c ? v (side a) is the minimum difference between the output logic low level of the driving device and the input logic threshold. 4. side a measured at 0.6 v.
rev. 1.2 7 si860x table 4. electrical characteristics for unidirectional non-i 2 c digital channels (si8602/05/06) 3.0 v < vdd < 5.5 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test condition min typ max unit positive-going input threshold vt+ all inputs rising 1.4 1.67 1.9 v negative-going input threshold vt? all inputs falling 1.0 1.23 1.4 v input hysteresis v hys 0.38 0.44 0.50 v high level input voltage v ih 2.0 ? ? v low level input voltage v il ??0 . 8v high level output voltage v oh loh = ?4 ma avdd, bvdd ?0.4 4.8 ? v low level output voltage v ol lol = 4 ma ? 0.2 0.4 v input leakage current i l ?? 1 0 a output impedance 1 z o ?5 0? ? timing characteristics maximum data rate 0 ? 10 mbps minimum pulse width ? ? 40 ns propagation delay t phl , t plh see figure 1 ? ? 20 ns pulse width distortion |t plh ? t phl | pwd see figure 1 ? ? 12 ns propagation delay skew 2 t psk(p-p) ? ? 20 ns channel-channel skew t psk ? ? 10 ns output rise time t r c 3 =15pf see figure 1 and figure 2 ?2.54.0ns output fall time t f c 3 =15pf see figure 1 and figure 2 ?2.54.0ns peak eye diagram jitter t jit(pk) ? 350 ? ps notes: 1. the nominal output impedance of a non-i 2 c isolator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination re sistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a fa ctor, output pins should be appropriately terminated with controlled impedance pcb traces. 2. t psk(p-p) is the magnitude of the difference in propagation delay times measured between different units operating at the same supply voltages, lo ad, and ambient temperature.
8 rev. 1.2 si860x figure 1. propagation delay timing (non-i 2 c channels) table 5. electrical characteristics for all i 2 c and non-i 2 c channels 3.0 v < vdd < 5.5 v. ta = ?40 to +125 c. typical specs at 25 c parameter symbol test condition min typ max unit vdd undervoltage threshold vdduv+ v dd1 , v dd2 rising 1.95 2.24 2.375 v vdd undervoltage threshold vdduv? v dd1 , v dd2 falling 1.88 2.16 2.325 v vdd negative-going lockout hysteresis vdd hys 50 70 95 mv common mode transient immunity cmti v i =v dd or 0 v 35 50 ? kv/s shut down time from uvlo t sd ?3.0? s start-up time * t start ?1540s *note: start-up time is the time period from the appl ication of power to valid data at the output. typical input t plh t phl typical output t r t f 90% 10% 90% 10% 1.4 v 1.4 v
rev. 1.2 9 si860x 1.1. test circuits figure 2 depicts the timing test diagram. figure 2. simplified timing test diagram table 6. regulatory information* csa the si860x is certified under csa component acceptanc e notice 5a. for more details, see file 232873. 61010-1: up to 600 v rms reinforced insulation working voltage; up to 600 v rms basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working volt- age. 60601-1: up to 125 v rms reinforced insulation working voltage; up to 380 v rms basic insulation working voltage. vde the si860x is certified according to iec 60747-5-2. for more details, see file 5006301-4880-0001. 60747-5-2: up to 1200 v peak for basic insulation working voltage. 60950-1: up to 600 v rms reinforced insulation working voltage; up to 1000 v rms basic insulation working volt- age. ul the si860x is certified under ul15 77 component recognition program. for more details, see file e257455. rated up to 5000 v rms isolation voltage for basic protection. *note: regulatory certifications apply to 3.75 kv rms rated devices which are production tested to 4.5 kv rms for 1 sec. regulatory certifications apply to 5.0 kv rms rated devices which are production tested to 6.0 kv rms for 1 sec. for more information, see "6.ordering guide" on page 26. avdd nc bvdd nc nc nc adout bdin asda bsda ascl bscl adin bdout agnd bgnd si8605 c 1 c 1 c 3 r 1 r 1 r 2 r 2 c 3 c 2 c 2
10 rev. 1.2 si860x table 7. insulation and safety-related specifications parameter symbol test condition value unit nb soic-8 nb soic-16 wb soic-16 nominal air gap (clearance) 1 l(1o1) 4.9 4.9 8.0 mm nominal external tracking (creepage) 1 l(1o2) 4.01 4.01 8.0 mm minimum internal gap (internal clearance) 0.011 0.011 0.014 mm tracking resistance (proof tracking index) pti iec60112 600 600 600 v rms erosion depth ed 0.040 0.019 0.019 mm resistance (input-output) 2 r io 10 12 10 12 10 12 ? capacitance (input-output) 2 c io f = 1 mhz 1.0 2.0 2.0 pf input capacitance 3 c i non-i 2 c channel 4.0 4.0 4.0 pf i 2 c channel 10 10 10 pf notes: 1. vde certifies the clearance and creepa ge limits as 4.7 mm minimum for the nb soic-8 and soic-16 packages and 8.5 mm minimum for the wb soic-16 package. ul does not impose a clearance and creepage minimum for component level certifications . csa certifies the clearance and creepage li mits as 3.9 mm minimum for the nb soic-8 and soic-16 packages and 7.6 mm minimum for the wb soic-16 package. 2. to determine resistance and capacitance, the si860x, so-16, is co nverted into a 2-terminal device. pins 1?8 (1?4, so- 8) are shorted together to fo rm the first terminal and pins 9?16 (5?8, so -8) are shorted together to form the second terminal. the parameters are then measured between these two terminals. 3. measured from input pin to ground. table 8. iec 60664-1 (vde 0844 part 2) ratings parameter test conditions specification nb soic-8 soic-16 wb soic-16 basic isolation group material group i i installation classification rated mains voltages < 150 v rms i-iv i-iv rated mains voltages < 300 v rms i-iii i-iv rated mains voltages < 400 v rms i-ii i-iii rated mains voltages < 600 v rms i-ii i-iii
rev. 1.2 11 si860x table 9. iec 60747-5-2 insulation characteristics for si86xxxx* parameter symbol test condition characteristic unit wb soic-16 nb soic-8 soic-16 maximum working insulation voltage v iorm 1200 630 vpeak input to output test voltage v pr method b1 (v iorm x1.875=v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc) 2250 1182 vpeak transient overvoltage v iotm t = 60 sec 6000 6000 vpeak pollution degree (din vde 0110, table 1) 22 insulation resistance at t s , v io =500v r s >10 9 >10 9 ? *note: maintenance of the safety data is ensu red by protective circuits. the si86xxxx provides a climate classification of 40/125/21. table 10. iec safety limiting values 1 parameter symbol test condition nb soic-8 nb soic-16 wb soic-16 unit case temperature t s 150 150 150 c safety input current i s ? ja = 100 c/w (wb soic-16), 105 c/w (nb soic-16), 140 c/w (nb soic-8) avdd, bvdd = 5.5 v, t j =150c, t a =25c 160 210 220 ma device power dissipation 2 p d 220 275 275 w notes: 1. maximum value allowed in the event of a failure. refer to the thermal derating curve in figures 3, 4, and 5. 2. the si86xx is tested with avdd, bvdd = 5.5 v; t j =150oc; c 1 , c 2 =0.1f; c 3 = 15 pf; r1, r2 = 3k ??? input 1 mhz 50% duty cycle square wave.
12 rev. 1.2 si860x figure 3. nb soic-8 thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 figure 4. nb soic-16 thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 11. thermal characteristics parameter symbol test condition nb soic-8 nb soic-16 wb soic-16 unit ic junction-to-air thermal resistance ? ja 140 105 100 c/w 0 200 150 100 50 400 200 100 0 case temperature (oc) safety-limiting values (ma) 300 avdd, bvdd = 3.6 v avdd, bvdd = 5.5 v 270 160 02 0 0 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 300 350 210 avdd , bvdd = 3.6 v avdd , bvdd = 5.5 v
rev. 1.2 13 si860x figure 5. wb soic-16 thermal derating curve, dependence of safety limiting values with case temperature per din en 60747-5-2 table 12. absolute maximum ratings 1 parameter symbol min typ max unit storage temperature 2 t stg ?65 ? 150 oc ambient temperature under bias t a ?40 ? 125 oc junction temperature t j ??150c supply voltage v dd ?0.5 ? 7.0 v input voltage v i ?0.5 ? v dd + 0.5 v output voltage v o ?0.5 ? v dd + 0.5 v output current drive (non-i 2 c channels) i o ??10ma side a output current drive (i 2 c channels) i o ??15ma side b output current drive (i 2 c channels) i o ??75ma lead solder temperature (10 s) ? ? 260 oc maximum isolation (input to output) (1 sec) nb soic-8, soic-16 ? ? 4500 v rms maximum isolation (input to output) (1 sec) wb soic-16 ? ? 6500 v rms notes: 1. permanent device damage may occur if the absolute maximum ratings are exceeded. functional operation should be restricted to conditions as specified in the operational sections of this data sheet. 2. vde certifies storage temper ature from ?40 to 150 c. 02 0 0 150 100 50 500 400 200 100 0 temperature (oc) safety-limiting current (ma) 300 350 220 avdd , bvdd = 3.6 v avdd , bvdd = 5.5 v
14 rev. 1.2 si860x 2. functional description 2.1. theory of operation the operation of an si86xx channel is analogous to that of an opto coupler, except an rf carrier is modulated instead of light. this simple archit ecture provides a robust isolated data path and requires no special considerations or initialization at st art-up. a simplified block diagram for a single unidirectional si86xx channel is shown in figure 6. figure 6. simplified channel diagram a channel consists of an rf transmitter and rf receiver separated by a semiconductor-based isolation barrier. referring to the transmitter, input a modulates the carrier provided by an rf oscillator using on/off keying. the receiver contains a demodulator that decodes the input state according to its rf energy content and applies the result to output b via the output driv er. this rf on/off keying scheme is superior to pulse code schemes as it provides best-in-class noise immunity, low power consum ption, and better immunity to magnetic fields. see figure 7 for more details. figure 7. modulation scheme rf oscillator modulator demodulator a b semiconductor- based isolation barrier transmitter receiver input signal output signal modulation signal
rev. 1.2 15 si860x 3. typical application overview 3.1. i 2 c background in many applications, i 2 c, smbus, and pmbus interfaces require galvanic isolation for safety or ground loop elimination. for example, power over ether net (poe) applications typically use an i 2 c interface for communication between the poe power sourcing device (pse), and the earth ground referenced system controller. galvanic isolation is required both by standard and also as a prac tical matter to prevent ground loops in ethernet connected equipment. the physical interface consists of tw o wires: serial data (sda) and serial clock (scl). these wires are connected to open collector drivers that serve as both inputs and out puts. at first glance, it appears that sda and scl can be isolated simply by placing two unidirectional isolators in parallel, and in opposite directions. however, this technique creates feedback that latches the bus line low when a logic low asserted by ei ther master or slave. this problem can be remedied by adding anti-latch circuits, bu t results in a larger and more expensive solution. the si860x products offer a single-chip, anti-l atch solution to the problem of isolating i 2 c/smbus applications and require no external components except the i 2 c/smbus pull-up resistors. in addi tion, they provide isolation to a maximum of 5.0 kv rms , support i 2 c clock stretching, and operate to a maximum i 2 c bus speed of 1.7 mbps. 3.2. i 2 c isolator operation without anti-latch protection, bidirectional i 2 c isolators latch when an isolator output logic low propagates back through an adjacent isolator channel creating a stable latched low condition on both sides. anti-latch protection is typically added to one side of the is olator to avoid this condition (the ?a? side for the si8600/02/05/06). the following examples illustrate typical circui t configurations using the si8600/02/05/06. figure 8. isolated bus overview (i 2 c channels only) the ?a side? output low (v ol ) and input low (v il ) levels are designed such that the isolator v ol is greater than the isolator v il to prevent the latch condition. i 2 c/smbus unit 1 si8600/02/05/06 i 2 c/smbus unit 2 iso1 iso2 v ol v il + - v ol v il a side b side
16 rev. 1.2 si860x 3.3. i 2 c isolator design constraints table 13 lists the i 2 c isolator design constraints. 3.4. i 2 c isolator design considerations the first step in applying an i 2 c isolator is to choose which side of the bus will be connected to the isolator a side. ideally, it should be the side which: 1. is compatible with the range of bus pull up specified by the manufacturer. for example, the si8600/02/05/06 isolators are normally used with a pull up of 0.5 ma to 3 ma. 2. has the highest input low level for devices on the bu s. some devices may specif y an input low of 0.9 v and other devices might require an input low of 0.3 x vdd. assuming a 3.3 v minimum power supply, the side with an input low of 0.3 x vdd is the better side bec ause this side has an input low level of 1.0 v. 3. have devices on the bus that can pull down below the is olator input low level. for example, the si860x input level is 0.41 v. as most cmos devices can pull to within 0.4 v of gnd this is generally not an issue. 4. has the lowest noise. due to the special logi c levels, noise margins can be as low as 50 mv. table 13. design constraints design constraint data sheet values effect of bus pull-up strength and temperature to prevent the latch condition, the isolator output low level must be greater than the isolator input low level. isolator v ol 0.7 v typical isolator v il 0.5 v typical input/output logic low level difference ? vsda1, ? vscl1 = 50 mv minimum this is normally guaranteed by the isolator data sheet. however, if the pull up strength is too weak, the out- put low voltage will fall and can get too close to the input low logic level. these track over temperature. the bus output low must be less than the isolator input low logic level. bus v ol =0.4v maximum isolator v il = 0.41 v minimum if the pull up streng th is too large, the devices on the bus might not pull the voltage below the input low range. these have opposite temper- ature coefficients. worst case is hot temperature. the isolator output low must be less than the bus input low. bus v il 0.3 x v dd = 1.0 v minimum for v dd =3.3v isolator v ol = 0.8 v maximum if the pull up streng th is too large, the isolator might not pull below the bus input low voltage. si8600/02/05/06 vol: ?1.8 mv/c cmos buffer: ?0.6 mv/c this provides some temperature tracking, but worst case is cold tem- perature.
rev. 1.2 17 si860x 3.5. typical appl ication schematics figures 9 through 14 illustra te typical circuit configurations using the si8600, si8602, si8605, and si8606. figure 9. typical si8600 application diagram figure 10. typical si8602 application diagram figure 11. typical si8600 application diagram 1 2 7 si8600 3 8 avdd asda ascl agnd bgnd bscl bsda bvdd 3k 3k 0.1 f 0.1 f 3k 3k i 2 c bus 6 5 4 1 2 7 si8602 3 8 avdd asda ascl agnd bgnd bscl bsda bvdd 3k 0.1 f 0.1 f 3k i 2 c bus 6 5 4 1 2 3 4 5 6 7 15 14 13 12 11 10 8 9 si8600 3 16 avdd asda ascl agnd bgnd bscl bsda bvdd 3k 3k 0.1 f 0.1 f 3k 3k i 2 c bus agnd bgnd
18 rev. 1.2 si860x figure 12. typical si8602 application diagram figure 13. typical si8605 application diagram figure 14. typical si8606 application diagram 1 2 3 4 5 6 7 15 14 13 12 11 10 8 9 si8602 3 16 avdd asda ascl agnd bgnd bscl bsda bvdd 3k 0.1 f 0.1 f 3k i 2 c bus agnd bgnd 1 2 3 4 5 6 7 15 14 13 12 11 10 8 9 si8605 3 16 avdd asda ascl agnd micro- controller micro- controller bgnd bscl bsda bvdd 3k 3k 0.1 f 0.1 f 3k 3k i 2 c bus reset int 1 2 3 4 5 6 7 15 14 13 12 11 10 8 9 si8606 3 16 avdd asda ascl agnd micro- controller bgnd bscl bsda bvdd 3k 3k 0.1 f 0.1 f 3k 3k i 2 c bus reset int
rev. 1.2 19 si860x 4. device operation device behavior during start-up, normal operation, and shutdown is shown in figure 15, where uvlo+ and uvlo- are the positive-going and negative-going thresholds resp ectively. refer to table 14 to determine outputs when power supply (vdd) is not present. 4.1. device startup outputs are held low during powerup until vdd is above the uvlo threshold for time period tstart. following this, the outputs follow the states of inputs. 4.2. undervoltage lockout undervoltage lockout (uvlo) is provided to prevent erroneous operation during device startup and shutdown or when vdd is below its specified operating circuits range. both side a and side b each have their own undervoltage lockout monitors. each side can enter or exit uvlo independently. for example, side a unconditionally enters uvlo when avdd falls below avdd uvlo? and exits uvlo when avdd rises above avdd uvlo+ . side b operates the same as side a with respect to its bvdd supply. figure 15. device behavior during normal operation input avdd uvlo- bvdd uvlo+ uvlo- uvlo+ output tstart tstart tstart tphl tplh tsd
20 rev. 1.2 si860x 4.3. input and output characteristics for non-i 2 c digital channels the unidirectional si86xx inputs and outputs are standard cmos drivers/receivers. the nominal output impedance of an isolator driver channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series termination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appr opriately terminated with controlled im pedance pcb traces. table 14 details powered and unpowered operation of the si86xx?s non-i 2 c digital channels. table 14. si86xx operation table v i input 1,4 vddi state 1,2,3 vddo state 1,2,3 v o output 1 ,4 comments hp p h normal operation. lp p l x 5 up p l 6 h 6,7 upon transition of vddi from unpowered to pow- ered, v o returns to the same state as v i in less than 1 s. x 5 p up undetermined upon transition of vddo from unpowered to pow- ered, v o returns to the same state as v i within 1s. notes: 1. vddi and vddo are the input and output power supplies. v i and v o are the respective input and output terminals. 2. powered (p) state is defined as 3.0 v < vdd < 5.5 v. 3. unpowered (up) state is defined as vdd = 0 v. 4. x = not applicable; h = logic high; l = logic low. 5. note that an i/o can power the die for a given side through an internal diode if its source has adequate current. 6. see "6.ordering guide" on page 26 for details. this is the selectable fail-safe operating mode (ordering option). some devices have default output state = h, and some have defaul t output state = l, depending on the ordering part number (opn). for default high devices, the data channels have pull-ups on inputs/outputs. for default low devices, the data channels have pull-downs on inputs/outputs. 7. for i 2 c channels, the outputs for a given side go to hi-z when power is lost on the opposite side.
rev. 1.2 21 si860x 4.4. layout recommendations to ensure safety in the end us er application, high voltage circ uits (i.e., circuits with >30 v ac ) must be physically separated from the safety extra-low voltage circuits (selv is a circuit with <30 v ac ) by a certain distance (creepage/clearance). if a component, su ch as a digital isolator, straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection). t able 6 on page 9 and table 7 on page 10 detail the working voltage and creepage/clearance capab ilities of the si86xx. these tables also detail the co mponent standards (ul1577, iec60747, csa 5a), which ar e readily accepted by ce rtification bodies to pr ovide proof for end-system specifications requirements. refer to the end-system spec ification (61010-1, 60950-1, 60601-1, etc.) requirements before starting any design that uses a digital isolator. 4.4.1. supply bypass the si860x family requires a 0.1 f bypass capaci tor between avdd and agnd and bvdd and bgnd. the capacitor should be placed as close as possible to the package. to enhance the robustness of a design, the user may also include resistors (50?300 ? ) in series with the inputs and outp uts if the system is excessively noisy. 4.4.2. output pin termination the nominal output impedance of an non-i 2 c isolator channel is approximately 50 ? , 40%, which is a combination of the value of the on-chip series term ination resistor and channel resistance of the output driver fet. when driving loads where transmission line effects will be a factor, output pins should be appr opriately terminated with controlled impedance pcb traces. 4.5. fail-saf e operating mode si86xx devices feature a selectable (by ordering option ) mode whereby the default ou tput state (when the input supply is unpowered) can either be a logic high or logi c low when the output supply is powered. see table 14 on page 20 and "6.ordering guide" on page 26 for more information.
22 rev. 1.2 si860x 4.6. typical perfor mance characteristics the typical performance characteristics de picted in the following diagrams are for information purposes only. refer to tables 2, 3, 4, and 5 fo r actual specification limits. figure 16. i 2 c side a pulling down (1100 ? pull-up) figure 17. i 2 c side b pulling down figure 18. i 2 c side b pulling up, side a following figure 19. i 2 c side a pulling up, side b following figure 20. non i 2 c channel propagation delay vs. temperature side b side a side b side a side b side a side b side a 5.0 6.0 7.0 8.0 9.0 10.0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100110120 delay (ns) temperature (degrees c)
rev. 1.2 23 si860x 5. pin descriptions table 15. si8600/02 in soic-8 package pin name description 1 avdd side a power supply terminal; connect to a source of 3.0 to 5.5 v. 2 asda side a data (open drain) input or output. 3 ascl side a clock input or output. open drain i/o for si8600. standard cmos input for si8602. 4 agnd side a ground terminal. 5 bgnd side b ground terminal. 6 bscl side b clock input or output. open drain i/o for si8600. push-pull output for si8602. 7 bsda side b data (open drain) input or output. 8 bvdd side b power supply terminal; connect to a source of 3.0 to 5.5 v. bidirectional isolator channel bidirectional isolator channel asda bsda ascl bscl agnd bgnd avdd bvdd si8600 1 2 3 4 8 7 6 5 bidirectional isolator channel unidirectional isolator channel asda bsda ascl bscl agnd bgnd avdd bvdd si8602 1 2 3 4 8 7 6 5
24 rev. 1.2 si860x table 16. si8600/02 in narrow and wide-body soic-16 packages pin name description 1 agnd side a ground terminal. 2 nc no connection. 3 avdd side a power supply terminal. conn ect to a source of 3.0 to 5.5 v. 4 nc no connection. 5 asda side a data open drain input or output. 6a s c l side a data open drain input or output. 7 agnd side a ground terminal. 8 nc no connection. 9 bgnd side b ground terminal. 10 nc no connection. 11 bscl side b data open drain input or output. 12 bsda side b data open drain input or output. 13 nc no connection. 14 bvdd side b power supply terminal. conn ect to a source of 3.0 to 5.5 v. 15 nc no connection. 16 bgnd side b ground terminal. bidirectional isolator channel avdd nc bvdd nc nc nc asda bsda ascl bscl si8602 agnd bgnd 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 nc agnd bgnd unidirectional isolator channel nc bidirectional isolator channel avdd nc bvdd nc nc nc asda bsda ascl bscl si8600 agnd bgnd bidirectional isolator channel 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 nc agnd bgnd nc
rev. 1.2 25 si860x table 17. si8605/06 in narrow and wide-body soic-16 packages pin name description 1 avdd side a power supply terminal. conn ect to a source of 3.0 to 5.5 v. 2 nc no connection. 3 asda side a data (open drain) input or output. 4adin/adin1 side a standard cmos digital input (non i 2 c). 5 adout/adin2 side a digital input/output (non i 2 c) standard cmos digital input for si8606. push-pull output for si8605. 6a s c l side a clock input or output. open drain i/o for si8605/06. 7 nc no connection. 8 agnd side a ground terminal. 9 bgnd side b ground terminal. 10 nc no connection. 11 bscl side b clock input or output. open drain i/o for si8605/06. 12 bdin/bdout2 side b digital input/output (non i 2 c) standard cmos digital input for si8605. push-pull output for si8606. 13 bdout/bdout1 side b digital push-pull output (non i 2 c). 14 bsda side b data open drain input or output. 15 nc no connection. 16 bvdd side b power supply terminal. conn ect to a source of 3.0 to 5.5 v. bidirectional isolator channel avdd nc bvdd nc nc nc adin2 bdout2 asda bsda unidirectional isolator channel ascl bscl adin1 bdout1 si8606 agnd bgnd unidirectional isolator channel bidirectional isolator channel 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 bidirectional isolator channel avdd nc bvdd nc nc nc adout bdin asda bsda unidirectional isolator channel ascl bscl adin bdout si8605 agnd bgnd unidirectional isolator channel bidirectional isolator channel 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16
26 rev. 1.2 si860x 6. ordering guide table 18. ordering guide 1,2 ordering part number (opn) number of bidirectional i 2 c channels max i 2 c bus speed (mhz) number of unidirectional non-i 2 c channels max data rate of non-i 2 c unidirectional channels (mbps) isolation ratings (kvrms) temp range ( ?c) package SI8600AC-B-IS 2 1.7 0 ? 3.75 ?40 to 125 nb soic-8 si8600ad-b-is 2 1.7 0 ? 5.0 ?40 to 125 wb soic-16 si8602ac-b-is 1 1.7 1 10 3.75 ?40 to 125 nb soic-8 si8602ad-b-is 1 1.7 1 10 5.0 ?40 to 125 wb soic-16 si8605ac-b-is1 2 1.7 1 forward 1 reverse 10 3.75 ?40 to 125 nb soic-16 si8605ad-b-is 2 1.7 1 forward 1 reverse 10 5.0 ?40 to 125 wb soic-16 si8606ac-b-is1 2 1.7 2 forward 1 0 3.75 ?40 to 125 nb soic-16 si8606ad-b-is 2 1.7 2 forward 10 5.0 ?40 to 125 wb soic-16 notes: 1. all packages are rohs-compliant with pea k reflow temperature of 260 c according to the jedec industry standard classifications and peak solder temperature. moisture sensitivity level is msl3 for wide-body soic-16 packages. moisture sensitivity level is msl2a for narrow-body soic-16 packages. moisture sensitivity level is msl2a for narrow-body soic-8 packages. 2. all devices >1 kv rms are aec-q100 qualified.
rev. 1.2 27 si860x 7. package outline: 16-pin wide body soic figure 21 illustrates the package details for the si860x digital isolator. table 19 lists the values for the dimensions shown in the illustration. figure 21. 16-pin wide body soic
28 rev. 1.2 si860x table 19. package diagram dimensions dimension min max a ? 2.65 a1 0.10 0.30 a2 2.05 ? b 0.31 0.51 c 0.20 0.33 d 10.30 bsc e 10.30 bsc e1 7.50 bsc e 1.27 bsc l 0.40 1.27 h 0.25 0.75 ? 0 8 aaa ?0 . 1 0 bbb ? 0.33 ccc ? 0.10 ddd ? 0.25 eee ? 0.10 fff ? 0.20 notes: 1. all dimensions shown are in mil limeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to jedec outline ms-013, variation aa. 4. recommended reflow profile per jede c j-std-020c specification for small body, lead-free components.
rev. 1.2 29 si860x 8. land pattern: 16-pin wide-body soic figure 22 illustrates t he recommended land pattern details for the si860x in a 16-pin wide-body soic. table 20 lists the values for the dimens ions shown in the illustration. figure 22. 16-pin soic land pattern table 20. 16-pin wide body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 9.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.90 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p1032x265-16an for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
30 rev. 1.2 si860x 9. package outline: 8-pin narrow body soic figure 23 illustrates the package details for the si860x in an 8- pin soic (so-8). table 21 lists the values for the dimensions shown in the illustration. figure 23. 8-pin small outline integrated circuit (soic) package table 21. package diagram dimensions symbol millimeters min max a 1.35 1.75 a1 0.10 0.25 a2 1.40 ref 1.55 ref b 0.33 0.51 c 0.19 0.25 d 4.80 5.00 e 3.80 4.00 e 1.27 bsc h 5.80 6.20 h 0.25 0.50 l 0.40 1.27 ? 0 ? 8 ? ?
rev. 1.2 31 si860x 10. land pattern: 8-pin narrow body soic figure 24 illustrates the recommended land pattern details for the si860x in an 8-pin narrow-body soic. table 22 lists the values for the dimens ions shown in the illustration. figure 24. pcb land pattern: 8-pin narrow body soic table 22. pcm land pattern dimensions (8-pin narrow body soic) dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x173-8n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
32 rev. 1.2 si860x 11. package outline: 16-pin narrow body soic figure 25 illustrates the package details for the si860x in a 16-pin narrow-b ody soic (so-16). table 23 lists the values for the di mensions shown in the illustration. figure 25. 16-pin small outline integrated circuit (soic) package
rev. 1.2 33 si860x table 23. package diagram dimensions dimension min max a ? 1.75 a1 0.10 0.25 a2 1.25 ? b 0.31 0.51 c 0.17 0.25 d 9.90 bsc e 6.00 bsc e1 3.90 bsc e 1.27 bsc l 0.40 1.27 l2 0.25 bsc h 0.25 0.50 0 8 aaa 0.10 bbb 0.20 ccc 0.10 ddd 0.25 notes: 1. all dimensions shown are in mill imeters (mm) unless otherwise noted. 2. dimensioning and tolerancing per ansi y14.5m-1994. 3. this drawing conforms to the jedec solid state outline ms-012, variation ac. 4. recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components.
34 rev. 1.2 si860x 12. land pattern: 1 6-pin narrow body soic figure 26 illustrates the recommended land pattern details for the si860x in a 16-pin narrow-body soic. table 24 lists the values for the dimens ions shown in the illustration. figure 26. 16-pin narrow body soic pcb land pattern table 24. 16-pin narrow body soic land pattern dimensions dimension feature (mm) c1 pad column spacing 5.40 e pad row pitch 1.27 x1 pad width 0.60 y1 pad length 1.55 notes: 1. this land pattern design is based on ipc-7351 pattern soic127p600x165-16n for density level b (median land protrusion). 2. all feature sizes shown are at maximum material condition (mmc) and a card fabrication tolerance of 0.05 mm is assumed.
rev. 1.2 35 si860x 13. top markings 13.1. si860x top marking (16-pin wide body soic) 13.2. top marking explanatio n (16-pin wide body soic) line 1 marking: base part number ordering options (see ordering guide for more information). si86 = isolator product series xy = channel configuration 05 = bidirectional scl, sda; 1- forward and 1-reverse unidirectional channel 06 = bidirectional scl, sda; 2- forward unidirectional channels s = speed grade a=1.7mbps v = isolation rating a = 1 kv; b = 2.5 kv; c = 3.75 kv; d = 5.0 kv line 2 marking: yy = year ww = workweek assigned by assembly subcontractor. corresponds to the year and workweek of the mold date. rttttt = mfg code manufacturing code from assembly house ?r? indicates revision line 3 marking: circle = 1.5 mm diameter (center-justified) ?e3? pb-free symbol country of origin iso code abbreviation tw = taiwan si86xysv yywwrttttt tw e3
36 rev. 1.2 si860x 13.3. si860x top marking (8-pin narrow body soic) 13.4. top marking explanatio n (8-pin narrow body soic) line 1 marking: base part number ordering options (see ordering guide for more information). si86 = isolator i 2 c product series: xy = channel configuration 00 = bidirectional scl and sda channels 02 = bidirectional sda channel; unidirectional scl channel s = speed grade a=1.7mbps v = isolation rating a = 1 kv; b = 2.5 kv; c = 3.75 kv line 2 marking: yy = year ww = work week assigned by assembly contractor. corresponds to the year and work week of the mold date. r = product rev f=wafer fab first two characters of the manufacturing code from assembly. line 3 marking: circle = 1.1 mm diameter left-justified ?e3? pb-free symbol a = assembly site i = internal code xx = serial lot number last four characters of the manufacturing code from assembly. si86xysv yywwrf aixx e3
rev. 1.2 37 si860x 13.5. si860x top marking (16-pin narrow body soic) 13.6. top marking explanatio n (16-pin narrow body soic) line 1 marking: base part number ordering options si86 = isolator product series xy = channel configuration 05 = bidirectional scl, sda; 1- forward and 1-reverse unidirectional channel 06 = bidirectional scl, sda; 2- forward unidirectional channels s = speed grade a=1.7mbps v = isolation rating a=1kv; b=2.5kv; c=3.75kv line 2 marking: circle = 1.2 mm diameter ?e3? pb-free symbol yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the mold date. rttttt = mfg code manufacturing code from assembly house ?r? indicates revision circle = 1.2 mm diameter ?e3? pb-free symbol. si86xysv yywwrttttt e3
38 rev. 1.2 si860x d ocument c hange l ist revision 0.1 to revision 0.2 ? si8601 replaced by si8602 throughout. ? added chip graphics on page 1. ? moved table 12 to page 13. ? updated table 3, ?si8600/02/05/06 electrical characteristics for bidirectional i2c channels 1 ,? on page 5. ? updated table 7, ?insulation and safety-related specifications,? on page 10. ? updated table 9, ?iec 60747-5-2 insulation characteristics for si86xxxx*,? on page 11. ? moved ?3. typical application overview? to page 15. ? moved ?typical performance characteristics? to page 22. ? updated "5.pin descriptions" on page 23. ? updated "6.ordering guide" on page 26. revision 0.2 to revision 0.3 ? added chip graphics on page 1. ? moved tables 1 and 2 to page 4. ? updated table 7, ?insulation and safety-related specifications,? on page 10. ? updated table 9, ?iec 60747-5-2 insulation characteristics for si86xxxx*,? on page 11. ? moved table 13 to page 16. ? moved table 14 to page 20. ? updated "5.pin descriptions" on page 23. ? updated "6.ordering guide" on page 26. revision 0.3 to revision 1.0 ? reordered spec tables to conform to new convention. ? removed ?pending? throughout document. revision 1.0 to revision 1.1 ? updated figures 11 and 12. ?? updated pin 7 agnd connection. ? updated "6.ordering guide" on page 26 to include msl2a. revision 1.1 to revision 1.2 ? updated table 12 on page 13. ?? added junction temperature spec. ? updated "4.4.1.supply bypass" on page 21. ? updated "6.ordering guide" on page 26. ?? removed rev a devices. ? updated "7.package outline: 16-pin wide body soic" on page 27. ? updated top marks. ?? added revision description.
rev. 1.2 39 si860x n otes :
40 rev. 1.2 si860x c ontact i nformation silicon laboratories inc. 400 west cesar chavez austin, tx 78701 tel: 1+(512) 416-8500 fax: 1+(512) 416-9669 toll free: 1+(877) 444-3032 please visit the silicon labs technical support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsib ility for any consequences resu lting from the use of information included herein. additionally, silicon laboratorie s assumes no responsibility for the functioning of undescribed features or parameters. silicon laboratories reserves the right to make changes without further notice . silicon laboratories makes no wa rranty, rep- resentation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon laboratories as sume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any an d all liability, including wi thout limitation conse- quential or incidental damages. silicon laborat ories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the silicon laboratories product could create a s ituation where per- sonal injury or death may occur. should buyer purchase or us e silicon laboratories products for any such unintended or unauthor ized ap- plication, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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